`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2022/10/08 20:55:19
// Design Name: 
// Module Name: ALU
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ALU(
    input [31:0] SrcA,
	input [31:0] SrcB,
	input [4:0] shamt,
	input [2:0] ALUOp,
	output Equ,
	output reg [31:0] result
    );
	assign Equ = (SrcA == SrcB) ? 1 : 0;
	always @(*) begin
		case (ALUOp)
		    3'b000: result = SrcA + SrcB;
		    3'b001: result = SrcA - SrcB;
		    3'b010: result = SrcA | SrcB;
		    3'b011: result = SrcA << shamt;
		    default: result = SrcA;
		endcase
	end
endmodule
